As leaders in development of ultra-low latency products to support trading, they strive to enhance collaboration amongst the global trading markets worldwide. The right candidate will be multi-faceted and excited for an opportunity to work with complex hardware in a challenging environment that provides extremely competitive compensation packages. The candidate will be part of a team actively working to rethink, redesign, and surpass the status quo.
Design Verification Engineer Responsibilities:
- Create detailed verification plans' architect & implement verification environments using leading-edge industry techniques
- Contribute to the continued development of the design productivity tooling & workflows
- Interpret high level requirements to create exceptional solutions for the trading community
- Collaborate with wider ASIC design team to facilitate rapid project convergence & execution
The Design Verification Engineer MUST have the following Requirements:
- Bachelor's Degree (ideally in Electrical Engineering, Computer Science/Engineering)
- 3+ years of Verification design experience
- Strong software/HDL development skills [C++, Python]
- Excellent debug and analytical skills to quickly root-cause RTL bugs - (in hardware & software environments)
- Ability to manage regression and continuous integration infrastructure.
Additional Qualifications are a plus:
- Demonstrated experience in complex verification environment [System Verilog, UVM, OVM, VMM]
- Professional hands-on experience working with Linux platforms.
- Familiarity with development infrastructure (HTML, MySQL)
- Experience with embedded software (assembly language, processor architecture)
If you are interested in the Design Verification Engineer role, please apply ASAP!