FPGA Verification Engineer Responsibilities:
- Creating testbenches and tests & writing detailed verification plans
- Adapting UVM principles to an open source-based, highly flexible verification environment
- Collaborating directly with designers for rapid bring up of new projects and debugging of existing designs.
- Managing regression and continuous integration infrastructure.
- Developing and improving open-source and internal tools.
The FPGA Verification Engineer MUST have the following Requirements: (financial industry experience NOT required)
- Bachelor's Degree (ideally in Electrical Engineering, Computer Science/Engineering)
- 5+ years of RTL verification experience - [utilizing either (System Verilog + UVM) OR Cocotb]
- Proficient utilizing one or more programming languages [Python, C++]
- Excellent debug and analytical skills to quickly root-cause RTL bugs
- Demonstrated experience working with code & functional coverage collection/analysis.
Additional Qualifications are a plus:
- Professional hands-on experience working with Linux platforms.
- Familiarity with Verilator and/or Cocotb
- Experience with networking protocols (Ethernet, IP, TCP, UDP)
- Demonstrated experience in complex verification environment [System Verilog, UVM, OVM, VMM]
If you are interested in the FPGA Engineer role, please apply ASAP!